1. Field of the Invention
The present invention relates to a circuit of sensing a fuse cell in a flash memory, and more particularly to a circuit of sensing a fuse cell in a flash memory which can latch stably a data stored on a fuse cell(Content Address Memory-CAM) at the time of power-on of a flash memory, by deciding time setup for sensing and latching a data on the fuse cell by a reference circuit and by tracking the sensing time due to process change by the reference circuit, in reading and latching fuse cell data at the time of power-on of the memory.
2. Description of the Prior Art
Typically, technology for latching data on a fuse cell at the time of power-on of a flash memory is already known for VLSI design in the repair circuit of a flash memory.
FIG. 1 is a circuit diagram of sensing a fuse cell in a flash memory according to a prior art.
Operation of FIG. 1 will be described with reference to FIGS. 2A and 2B.
If supply voltage Vcc is power-up at zero(0) volt (t1 of FIG. 2A), the initial voltage level of the first node K1 becomes the virtual ground(threshold voltage of transistor N1) by an NMOS transistor N1 in the power-on reset circuit 1, and the capacitor C1 is not charged at the initial stage. However, during the supply voltage Vcc rises, the capacitor C1 is gradually charged by the current flowing through a PMOS transistor P1. As the PMOS transistor P1 is small and the capacitor C1 is very large, electric potential of the first node K1 keeps a low state because the potential rises more slowly than ramp up speed of the supply voltage until it becomes higher than a specified threshold voltage Vt of the inverter I1. The electric potential of the output node K2 in the power-on reset circuit 1, which is the output of the inverter I1, keeps the high state, and allows the NMOS transistor N3 turned on. The word line voltage is applied to the gate electrode of the fuse cell M1 by the word line decoder circuit 2 and the fuse cell M1 is selected.
For example, current flowing to the ground terminal Vss is cut off by the fuse cell M1 if the fuse cell M1 is programmed normally. Then, the NMOS transistor N2, of which a gate electrode is applied with the supply voltage Vcc, is turned on, and potential of the bit line BL becomes high state by the PMOS transistor P2. Voltage of the bit line is applied to the inverter I2 of the latch circuit 3 through the NMOS transistor N3, and output of the above inverter I2 is latched to be low. Output of the inverter I2 is inverted to be high by the inverter I4, and is output through the output terminal Vout(out 1 of FIG. 2A).
On the contrary, if the fuse cell M1 is at the erase state, current pass is made to the ground terminal Vss by the fuse cell M1. Though the NMOS transistor N2, of which a gate electrode is applied with the supply voltage Vcc, is turned on and potential of the bit line BL becomes high by the PMOS transistor P2, current pass is made to the ground terminal by the fuse cell M1 and the potential of the bit line BL becomes low. The bit line voltage is input to the inverter I2 of the latch circuit 3 through the NMOS transistor N3, and the output of the inverter I2 is latched to the high state. Then, the output of the latch circuit 3 is inverted to the low state through the inverter I4, and is output through the output terminal Vout(out 2 of FIG. 2A).
In addition, when the supply voltage Vcc is higher than a predetermined voltage and the first node k1 becomes the high state, the electric potential of the output node K2 in the power-on reset circuit 1, which is the output of the inverter I1, keeps the low state and the NMOS transistor N3 is turned off. Thus, the fuse cell M1 and the latch circuit 3 are separated from each other.
Namely, as shown in FIG. 2B, if the time(t1) that the voltage is higher than a predetermined threshold voltage Vt of the inverter I1 passes, the electrical potential of the first node K1 becomes a high state, and the electrical potential of the output node K2 in the power-on reset circuit 1, which is the output of the inverter I1, becomes a low state.
However, as word line voltage is applied continuously to the gate electrode of the fuse cell M1 by the word line decoder circuit 2, it causes gate stress of the fuse cell M1. Thus, there is a problem in that charge capacity of the fuse cell M1 is lost because of the above reason.
It is necessary to minimize gate stress of a fuse cell by making the gate voltage needed for a sensing fuse cell sensing down to 0 V at the time of power-on(or after power-on).
FIG. 3A is a circuit diagram to solve the above problem. Its operation may be described with reference to FIG. 3B.
The voltage of an node K2, the output of the power-on reset circuit 1, is applied to the delay circuit 4. Word line voltage, the output voltage of the delay circuit 4, is applied to the gate electrode of the fuse cell M1. When voltage of the node K2, the output of the power-on reset circuit 1, becomes a low state, the word line voltage applied to the gate electrode of the fuse cell M1 is delayed for a predetermined time by the delay circuit 4 and then blocked(t1 to t2 in FIG. 3B).
However, such technology is the method to execute sensing of a fuse cell M1 for a predetermined time, using the power-on reset signals generated in the power-on reset circuit 1 at the time of power-on of a device. The time for sensing and latching a fuse cell M1 is fixed to a specified value by device designer at the time of design. Sometimes the case occurs that it is impossible to sense a fuse cell within the specified time designated in designing due to the cell current of a flash EEPROM cell for process change, and changes in threshold voltage and transistor characteristics.
Namely, if the word line voltage applied to the gate electrode of the fuse cell becomes the voltage not enough for sensing the memory state, the latch circuit 3 can not execute latching the data in the fuse cell M1.
Although the capacity of the PMOS transistor P2 and the ratio of the memory cell current(Ids) depending on the word line voltage applied to the gate electrode of the fuse cell M1 is suitable for sensing, it is impossible to latch the data of a memory cell to the latch circuit 3 even though the gate voltage of the fuse cell M1 is high, if the memory cell Vt and the turn-on current changes by process, as the size of the PMOS transistor P2, the threshold voltage of the inverter I1 and delay time by the delay circuit 4 is already defined at the time of designing a memory cell.